Design of Threshold Logic Flip-Flops for Achieving Efficient Performance of System

The approach is based on a design of threshold logic gates (TLGs) and their seamless integration with conventional standard-cell design flow. We first describe a new robust, standard-cell library of configurable circuits for implementing threshold functions. Abstractly, the threshold gate behaves as a multi-input, single output, edge-triggered flip-flop, which computes a threshold function of the inputs on the clock edge. The resulting circuits, with both conventional and TLGs (called hybrid circuits), are placed and routed using commercial tools. The design shows significant reductions (using post layout simulations) in power, leakage, and area of the hybrid circuits when compared with the conventional logic circuits, when both are operated at the maximum possible frequency of the conventional design.